The present invention relates to a structure of a Metal Insulator Semiconductor Field Effect Transistor (denoted as MIS FET hereinafter). In particular, the present invention relates to a structure to reduce a leakage current caused by a parasitic transistor formed adjacent to an active region of the MIS FET.
Among FET semiconductor devices, MIS FETs (when an oxide film is used as the insulator, it is called as MOS FET) are frequently used. In order to get a large amount of output current from the MIS FET, it is necessary to design the device with a large gate width. For this reason many designs can be used.
When the MIS FET is incorporated in an IC (Integrated Circuit), interconnection wirings to the source and the drain electrodes are formed on a dielectric film formed over a substrate. In some cases, part of the wiring adjacent to the active region of the MIS FET induces an inversion layer beneath the surface of the substrate and forms a parasitic transistor which collaborates with the drain and source regions of the MIS FET.
If a high voltage is applied to the drain wiring, it induces the inversion layer, and the parasitic transistor gives rise to a leakage current. The present invention provides a pattern for a gate electrode which suppresses the above mentioned leakage current.
An example of a MIS FET of the prior art is shown in FIG. 1. FIG. 1A is a top view of twin MIS FETs having a common source, and FIG. 1B and FIG. 1C show cross-sectional views taken along chained lines X--X' and Y--Y' in FIG. 1A respectively.
The invention will be described hereinafter with respect to the twin MIS FETs, but it will be apparent to anyone skilled in the art that, it is not limited to such a structure and the invention is applicable to any type of FETs.
In FIG. 1, an n.sup.- type substrate 1 is used, and a field oxide film 2 is formed on a surface of the substrate 1. The field oxide film 2 has an opening for an active region 3 of the MIS FET, which comprises a source region 4, two drain regions 5 and 5', and two channel regions 6 and 6'.
The channel regions 6 and 6' are covered with gate insulating films 7 and 7' respectively (they are usually oxide films), and polycrystalline silicone gate electrode 8 and 8' are formed thereon. The source and drain regions are formed by an ion implantation technique, for example, using the field oxide film 2 and the gate electrodes 8 and 8' as a mask. In this case, p.sup.+ type impurities are implanted into the MIS FET active region 3, and the p.sup.+ type regions of source and drain are formed.
After the formation of the source and drain regions, an insulating layer 9, a PSG (Phospho Silicate Glass) layer, for example, is formed by a CVD (Chemical Vapor Deposition) method. Contact windows 12 for the source and drain electrodes are formed in the insulating layer 9.
Subsequently an aluminum layer is deposited all over the surface of the substrate so that a source electrode 10, a source wiring 10', two drain electrodes 11 and a drain wiring 11' are formed by a selective etching process using photolithographic techniques.
The above mentioned MIS FET structure shown in FIG. 1 has two drain regions 5 and 5', one common source region 4 and two channel regions 6 and 6'. This design allows a large source to drain current I.sub.DS and consequently creates a large transconductance g.sub.m suitable for a p channel open-drain output circuit.
When the p channel MIS FET mentioned above is used in a driving circuit for a flourescent display tube, for example, a negative voltage of about -35 volts is supplied to the drain wiring 11'. FIG. 2 shows a circuit diagram of such an application.
In FIG. 2, Tr is a p channel MIS FET assembled in an IC 20; Dsp is a fluorescent display tube driven by IC 20, an anode electrode 21 of the display tube Dsp is connected to the output of the FET Tr, of which source, drain and gate electrodes are represented by S, D and G respectively. A negative terminal of a power supply 24 is connected to a center tap of a transformer 27, which is connected to a heater 22 of Dsp, via Zener diode 25, and is also connected to the drain D of Tr via a register 26. A connection of a grid electrode 23 of Dsp is not shown for simplicity.
When the MIS FET Tr is conductive a voltage drop of only a few volts occurs between the source S and drain D of the MIS FET Tr. Most of the voltage from the power supply 24 is applied to the fluorescent display tube Dsp.
When the gate voltage of Tr is driven to a cut off level, the voltage of the power supply is applied to the drain D of the MIS FET Tr. As shown in FIG. 2, when the negative voltage of the power supply 24 is -35 volts, for example, then the drain voltage of the MlS FET becomes almost -35 volts.
In FIG. 1A, when the voltage of drain wiring 11' becomes -35 volts, an inversion layer is formed on the cross shaded portion of the n.sup.- substrate beneath the drain wiring 11'. A channel 6" of the parasitic transistor Tr' is formed as shown in FIG. 1D, which shows a cross-sectional view taken along the dashed curve 14.
Dashed curves 14 and 14', shown with an arrow in FIG. 1A, indicate the directions of the current flow in the parasitic transistors as formed in the above example. The p channel parasitic transistor Tr', shown in FIG. 1D, is composed of a source region 4, a drain region 5, a channel region 6", a gate electrode 80 (an elongated portion of the gate electrode 8 which will be explained later) and drain wiring 11' as a second upper gate electrode. The current flowing in these parasitic transistors causes a current leakage in the main transistor Tr.
The current leakage due to the parasitic transistor Tr' mentioned above can be reduced by any one of the following methods. The first method is to elongate the gate electrodes 8 and 8' straight across the area so they extend out of the MIS FET active region 3 and extend into the region of the cross shaded portion 11' as shown by dashed lines 80 and 80' of the gate electrodes 8 and 8'. This method suppresses the current leakage to some degree because of the positive voltage from the gate electrodes 80 and 80'.
A second method of reducing current leakage is by forming a channel stopper in the area where the parasitic transistor Tr' is formed. The n.sup.+ channel stopper 16, shown by the rectangular shaped dashed line in FIG. 1A, is formed by the ion implantation technology in the early stages of wafer process. The n.sup.+ channel stopper 16 prevents the substrate from inducing the inversion layer.
The above mentioned methods to reduce the leakage current are conventionally used in the art, but these methods are still not sufficient to completely shut off the leakage current. Regarding the first method, if the voltage applied to the drain wiring 11' is high compared with that of the gate electrode 80, the gate electrode cannot totally prevent the formation of the inversion layer, and, as a result, the channel 6" of the parasitic transistor Tr' is formed.
In the second method of suppressing the leakage current by the channel stopper 16, the preferred method is to form the channel stopper 16 as close as possible to the active region 3 of the MIS FET. Usually the channel stopper is formed directly under the field oxide film 2 which is in contact with the active regions. This method is well known as the LOCOS method.
Moreover in a transistor that is required to operate at high voltage levels, the channel stopper cannot be provided close to the active region, because it decreases the break-down voltage at the p-n junction of the drain or source regions 5, 5', 4 to the channel stopper 16.
As shown in FIG. lA, the channel stopper 16 is formed in an opening window formed in the field oxide film 2 which is a short distance from the MIS FET active region 3. As a result of this configuration, the formation of the inversion layer and the resulting current leakage cannot be avoided.
The current leakage through the parasitic transistor will increase wasted power consumption and will cause the temperature of the MIS FET to rise. On the other hand, as a result of deterioration of the MIS FET characteristic the fluorescent display tube, for example, will continue to partially gleam on the display screen even when the MIS FET is cut off.